| Cadence Chip Planning System |
An enterprise-class IC planning and IP reuse environment designed for larger, global organizations needing the utmost in technical and economic estimation accuracy.? Provides support for estimation with custom IP and manufacturing processes. Features a co |
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| Cadence InCyte Chip Estimator |
Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and cost.? Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance techni |
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| Cadence Low-Power Methodology Kit |
将低功耗技术流程组成一个有机的系统，并优化其具体应用于。从而通过完整的前端到后端方法学，最佳的实践，检测表和参考流程来消除低功耗设计的风险。 |
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| Encounter Conformal Constraint Designer |
Automates the validation and refinement of constraints to ensure that timing constraints are valid throughout the entire design process. Identifies issues with clock-domain crossings early in the design process, helping designers achieve convergence on de |
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| Encounter Conformal ECO Designer |
Combines automatic ECO analysis, ECO logic optimization, and design netlist modification with the industry’s most trusted equivalence checking solution. Brings greater automation, predictability, and design convergence to pre- and post-mask ECOs. |
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| Encounter Conformal Equivalence Checker |
Handles large, complex datapaths, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs semantic and RTL linting checks. |
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| Encounter Conformal Low Power |
Enables the creation and validation of power intent in context of the design. Combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs. |
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| Encounter DFT Architect |
Minimizes test development and production costs. Delivers a flexible compression solution plus an integrated, power-aware methodology for specifying, inserting, and verifying full-chip production tests. |
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| Encounter RTL Compiler |
Allows engineers to concurrently optimize timing, area, power, and signal integrity intent. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation capability. |
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| Encounter RTL Compiler with Physical |
Enables logic designers to account for physical interconnect—-without the need to learn how to do physical design. |
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| Encounter Timing System |
Serves both front-end logic designers looking for high-quality static timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff. |
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| Encounter True-Time ATPG |
Automatically generates power- and timing-aware test patterns for small delay defects. Provides defect-based modeling capability with patented pattern fault technology, the basis for gate-exhaustive coverage. Supports stuck-at and transition fault models. |
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| Incisive Design Team Manager |
Drives verification closure using incrementally developed assertion and test list plans. Captures and quickly prioritizes failures. |
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| Incisive Design Team Simulator |
Supports full multi-language simulation including SystemVerilog. Provides comprehensive coverage (code, functional, transactional) and HDL analysis capabilities. |
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| Incisive Desktop Manager |
自动化和指导日常验证任务和结果的可视化。 |
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| Incisive Formal Verifier |
在验证环境可用之前，通过基于断言的验证进行形式化分析，检查RTL模块设计，来加速设计的收敛 |
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| Incisive Verification IP |
支持先进的测试平台，事务级的高层次的测试平台，基于断言的形式，模拟和加速模块级验证IP，以及仿真和在线仿真验证。包含多种复杂协议（PCI Express，AMBA，USB，OCP，以太网等）。 兼容OVM并支持各种IEEE标准语言。 |
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