Cadence SiP Digital Architect

品牌:Cadence
描述:Enables experimentation at the initial design stages for maximum functional density and performance.
包装:
封装:
无铅情况/ROHS: 有铅
经营商:科通芯城自营


Cadence® SiP Digital Architect manages the conceptual design flow from die to system-level SiP. It integrates with Encounter® digital design databases in a bi-directional flow for co-design optimization. SiP Digital Architect makes it possible to rapidly author a system-level SiP connectivity model for feasibility and verification studies. This enables engineers to maximize the functional density and performance of the package, and to minimize power consumption. SiP Digital Architect also performs IC I/O padring/array co-design with optimization capabilities at the IC, substrate, and system levels.

Features/Benefits
  • Speeds connectivity authoring and management with unique table and spreadsheet environment
  • Integrates with Encounter digital IC design technologies
  • Enables rapid system-level connectivity capture and “what-if” scenarios
  • Resolves design tradeoffs early in the flow for maximum performance
  • Completes I/O padring/array co-design with multi-level optimization
  • Supports bi-directional ECO and LVS flow for full co-design implementation
  • Performs feasibility and verification studies for design optimization
  • Allows RF and mixed-signal incorporation as hierarchical sub-blocksprofiles

文档(Document)

序号 PDF 描述
1 Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs     Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs
2 Cadence Chip-Package-Board Co-Design Solution Datasheet     Cadence Chip-Package-Board Co-Design Solution Datasheet
3 Cadence RF Design Methodology Kit Datasheet     Cadence RF Design Methodology Kit Datasheet
4 Cadence SiP Digital Design Datasheet     Cadence SiP Digital Design Datasheet
5 Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation     Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation
6 Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs     Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs
7 Use of System Link Design for Multi-Board Systems     Use of System Link Design for Multi-Board Systems

深圳市科通技术股份有限公司    客服电话:(+86)755-26018083    邮箱:cs@comtech.cn

© Copyright 2018 www.comtech.cn | 粤ICP备19161615号 | 粤公网安备 44030502003347号