处理器-酷睿处理器-AV80576LH0366M

参数	数值
# of Cores	2
# of Processing Die Transistors	410 million
# of Threads	2
Bus/Core Ratio	7.1
Clock Speed	1.86 GHz
Embedded Options Available	Yes
Enhanced Intel SpeedStep® Technology	Yes
Execute Disable Bit	Yes
FSB Parity	No
FSB Speed	1066 MHz
Idle States	No
Instruction Set	64-bit
Intel® 64	Yes
Intel® Demand Based Switching	No
Intel® Hyper-Threading Technology	No
Intel® Trusted Execution Technology	Yes
Intel® Turbo Boost Technology	No
Intel® Virtualization Technology (VT-x)	Yes
L2 Cache	6 MB
Launch Date	Q3'08
Lithography	45 nm
Low Halogen Options Available	See MDDS
Max TDP	17 W
Package Size	22mm x 22mm
Processing Die Size	107 mm 2
Processor Number	SL9400
Recommended Customer Price	TRAY: $284
Sockets Supported	BGA956
Status	Launched
Supplemental SKU	No
T JUNCTION	105°C
VID Voltage Range	1.050V - 1.150V

这些芯片组针对快速部署而优化，提供稍不相同的功能，有些经过英特尔® 酷睿™2 双核处理器 T9400^Δ、SL9400^Δ 和 SP9300^Δ、英特尔® 赛扬® M 处理器 722^Δ或英特尔® 赛扬® 处理器 575^Δ认证。它们在对温度要求较高的应用程序中提供了各种不同的高性能解决方案。

英特尔® 虚拟化技术： 允许硬件平台作为多个虚拟平台。
英特尔® 可信执行技术： 防止基于软件的攻击，并帮助保护数据。
英特尔® 64 架构： 支持 64 位指令。

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AV80576LH0366M

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序号	PDF	描述
1	"用于嵌入式计算的英特尔® 酷睿™ 2 双核处理器 T9400、P8400、SL9400、SL9380、SP9300、SU9300、T7500、 T7400、L7500、L7400 和 U7500 处	"用于嵌入式计算的英特尔® 酷睿™ 2 双核处理器 T9400、P8400、SL9400、SL9380、SP9300、SU9300、T7500、 T7400、L7500、L7400 和 U7500 处理器"
2	Application Note: Designing Embedded Systems for Testability	Application Note: Designing Embedded Systems for Testability
3	Datasheet: Intel® 82574 GbE Controller Family	Datasheet: Intel® 82574 GbE Controller Family
4	Datasheet: Intel® Celeron® Processor 900 Series and Ultra Low Voltage 700 Series	Datasheet: Intel® Celeron® Processor 900 Series and Ultra Low Voltage 700 Series
5	Datasheet: Intel® I/O Controller Hub 9 (ICH9) Family	Datasheet: Intel® I/O Controller Hub 9 (ICH9) Family
6	Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Mobile Processor, Intel®	Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Mobile Processor, Intel® Core™2 Extreme Mobile Processor on 45-nm Process
7	Intel® Core™2 Duo Processor and Intel® GM45 Express Chipset (with DDR2 System Memory) Development Ki	Intel® Core™2 Duo Processor and Intel® GM45 Express Chipset (with DDR2 System Memory) Development Kit User Manual
8	Intel® Core™2 Duo Processor and Intel® GM45 Express Chipset (with DDR3 System Memory) Development Ki	Intel® Core™2 Duo Processor and Intel® GM45 Express Chipset (with DDR3 System Memory) Development Kit User Manual
9	Intel® Core™2 Duo Processors on 45-nm Process Processor for Embedded Applications Thermal Design Gui	Intel® Core™2 Duo Processors on 45-nm Process Processor for Embedded Applications Thermal Design Guide
10	Mobile Intel® 4 Series Express Chipset Family	Mobile Intel® 4 Series Express Chipset Family
11	Power Profiling for Embedded Applications	Power Profiling for Embedded Applications
12	Presentation: Image Signal Processing Performance on 2nd Generation Core™ Microarchitecture	Presentation: Image Signal Processing Performance on 2nd Generation Core™ Microarchitecture
13	Product Brief: Intel® 82574L and 82574IT Gigabit Ethernet Controllers	Product Brief: Intel® 82574L and 82574IT Gigabit Ethernet Controllers
14	Product Brief: Intel® 82574L and 82574IT Gigabit Ethernet Controllers	Product Brief: Intel® 82574L and 82574IT Gigabit Ethernet Controllers
15	Solution Brief: Unwiring the Patient — Using Intel® technologies to create a wireless sensor platfor	Solution Brief: Unwiring the Patient — Using Intel® technologies to create a wireless sensor platform for hospitals
16	Specification Update: Intel® 4 Series Express Chipset	Specification Update: Intel® 4 Series Express Chipset
17	Specification Update: Intel® 82574 GbE Controller Family	Specification Update: Intel® 82574 GbE Controller Family
18	White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets	White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets
19	White Paper: Asymmetric Multi-Processing, Embedded and Communication MC Usage Model	White Paper: Asymmetric Multi-Processing, Embedded and Communication MC Usage Model
20	White Paper: Choosing the Right Storage Solution for Your Embedded Application	White Paper: Choosing the Right Storage Solution for Your Embedded Application
21	White Paper: Considerations for Designing an Embedded IA System with DDR3 SO-DIMMs	White Paper: Considerations for Designing an Embedded IA System with DDR3 SO-DIMMs
22	White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms	White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms
23	White Paper: Debugging Machine Check Exceptions on Embedded IA Platforms	White Paper: Debugging Machine Check Exceptions on Embedded IA Platforms
24	White Paper: Designing Systems without a Suspend Supply	White Paper: Designing Systems without a Suspend Supply
25	White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles	White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles
26	White Paper: Hardware Level I/O Benchmarking of PCI Express on Intel® Platforms	White Paper: Hardware Level I/O Benchmarking of PCI Express on Intel® Platforms
27	White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on I	White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on Intel® Architecture
28	White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on I	White Paper: How to Properly Measure Cache Latency, Memory Latency, and CPU to Memory Bandwidth on Intel® Architecture
29	White Paper: Interfacing I²C Devices to Intel's SMBus Controller	White Paper: Interfacing I²C Devices to Intel's SMBus Controller
30	White Paper: JTAG 101	White Paper: JTAG 101
31	White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization	White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization
32	White Paper: PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Cons	White Paper: PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Considerations
33	White Paper: Platform-Level error Handling Strategies for Intel® Systems	White Paper: Platform-Level error Handling Strategies for Intel® Systems
34	White Paper: Programming Models for Packet Processing Applications on Multi-Core Intel® Architecture	White Paper: Programming Models for Packet Processing Applications on Multi-Core Intel® Architecture Systems
35	White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts	White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts
36	White Paper: Seven Tips to Get Started on Embedded Multi-Core	White Paper: Seven Tips to Get Started on Embedded Multi-Core
37	White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines	White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines
38	White Paper: Thermal Design Considerations for Embedded Applications	White Paper: Thermal Design Considerations for Embedded Applications
39	White Paper: Upgrading to Multi-Core Ecosystem Keeps Car Simulator Running in the Fast Lane	White Paper: Upgrading to Multi-Core Ecosystem Keeps Car Simulator Running in the Fast Lane
40	White Paper: Using Intel® Processors for DSP Applications: Comparing the Performance of Freescale MP	White Paper: Using Intel® Processors for DSP Applications: Comparing the Performance of Freescale MPC8641D* and Two Intel® Core™2 Duo Processors
41	面向嵌入式计算的45 纳米英特尔® 赛扬®和	面向嵌入式计算的45 纳米英特尔® 赛扬®和
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44	支持嵌入式计算的移动式英特尔® GM45、GS45 和 GL40 高速芯片组	支持嵌入式计算的移动式英特尔® GM45、GS45 和 GL40 高速芯片组