序号 |
PDF |
描述 |
1 |
Application Note: Data Plane Packet Processing on Embedded Intel® Architecture Platforms
|
Application Note: Data Plane Packet Processing on Embedded Intel® Architecture Platforms |
2 |
Application Note: Designing Embedded Systems for Testability
|
Application Note: Designing Embedded Systems for Testability |
3 |
Case Study: Migrating the Ericsson* Operations Support System: RISC or Intel® based Servers
|
Case Study: Migrating the Ericsson* Operations Support System: RISC or Intel® based Servers |
4 |
Case Study: Putting VoIP Calls to the Test
|
Case Study: Putting VoIP Calls to the Test |
5 |
Datasheet: Intel® 5520 Chipset and Intel® 5500 Chipset
|
Datasheet: Intel® 5520 Chipset and Intel® 5500 Chipset |
6 |
Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller
|
Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller |
7 |
Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller
|
Datasheet: Intel® 82576 Gigabit Ethernet (GbE) Controller |
8 |
Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller
|
Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller |
9 |
Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller
|
Datasheet: Intel® 82599 10 Gigabit Ethernet (GbE) Controller |
10 |
Datasheet: Intel® I/O Controller Hub 10 (ICH10) Family
|
Datasheet: Intel® I/O Controller Hub 10 (ICH10) Family |
11 |
Datasheet: Intel® Xeon® Processor 5500 Series, Volume 1
|
Datasheet: Intel® Xeon® Processor 5500 Series, Volume 1 |
12 |
Datasheet: Intel® Xeon® Processor 5500 Series, Volume 2
|
Datasheet: Intel® Xeon® Processor 5500 Series, Volume 2 |
13 |
Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1
|
Design Guide: Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 |
14 |
Product Brief: Intel® 82576 Gigabit Ethernet Controller
|
Product Brief: Intel® 82576 Gigabit Ethernet Controller |
15 |
Product Brief: Intel® 82576 Gigabit Ethernet Controller
|
Product Brief: Intel® 82576 Gigabit Ethernet Controller |
16 |
Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity)
|
Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity) |
17 |
Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity)
|
Product Brief: Intel® 82599 10 Gigabit Ethernet Controller (Network Connectivity) |
18 |
Solution Brief: Integrating Services at the Edge: Test Results Show that One Intel® Xeon® Processor
|
Solution Brief: Integrating Services at the Edge: Test Results Show that One Intel® Xeon® Processor 5500 Series with Quad-core technology can forward traffic at 20 Gbps |
19 |
Solution Brief: The Right Computing Platform for Real-World Testing
|
Solution Brief: The Right Computing Platform for Real-World Testing |
20 |
Specification Update: Intel® 5520 Chipset and Intel® 5500 Chipsets
|
Specification Update: Intel® 5520 Chipset and Intel® 5500 Chipsets |
21 |
Specification Update: Intel® 82576 Gigabit Ethernet Controller
|
Specification Update: Intel® 82576 Gigabit Ethernet Controller |
22 |
Specification Update: Intel® 82576 Gigabit Ethernet Controller
|
Specification Update: Intel® 82576 Gigabit Ethernet Controller |
23 |
Specification Update: Intel® Xeon® Processor 5500 Series
|
Specification Update: Intel® Xeon® Processor 5500 Series |
24 |
Thermal & Mechanical Design Guidelines: Intel® 5520 and Intel® 5500 Chipsets
|
Thermal & Mechanical Design Guidelines: Intel® 5520 and Intel® 5500 Chipsets |
25 |
White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets
|
White Paper: Accessing PCI Express* Registers When Using Intel® Chipsets |
26 |
White Paper: Choosing the Right Storage Solution for Your Embedded Application
|
White Paper: Choosing the Right Storage Solution for Your Embedded Application |
27 |
White Paper: Consolidating Communications and Networking Workloads onto One Architecture
|
White Paper: Consolidating Communications and Networking Workloads onto One Architecture |
28 |
White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms
|
White Paper: DDR Signal Integrity (SI) Simulation Process for Intel® Architecture Platforms |
29 |
White Paper: Debugging Machine Check Exceptions on Embedded IA Platforms
|
White Paper: Debugging Machine Check Exceptions on Embedded IA Platforms |
30 |
White Paper: Designing Real-Time Solutions on Embedded Intel® Architecture Processors
|
White Paper: Designing Real-Time Solutions on Embedded Intel® Architecture Processors |
31 |
White Paper: Designing Systems without a Suspend Supply
|
White Paper: Designing Systems without a Suspend Supply |
32 |
White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles
|
White Paper: Embedded Intel® Architecture and High Speed Digital Design Principles |
33 |
White Paper: First the Tick, Now the Tock: Next Generation Intel® Microarchitecture (Nehalem)
|
White Paper: First the Tick, Now the Tock: Next Generation Intel® Microarchitecture (Nehalem) |
34 |
White Paper: High Performance Storage Encryption on Intel® Architecture Processors
|
White Paper: High Performance Storage Encryption on Intel® Architecture Processors |
35 |
White Paper: Improving OpenSSL* Performance
|
White Paper: Improving OpenSSL* Performance |
36 |
White Paper: Interfacing I²C Devices to Intel's SMBus Controller
|
White Paper: Interfacing I²C Devices to Intel's SMBus Controller |
37 |
White Paper: JTAG 101
|
White Paper: JTAG 101 |
38 |
White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization
|
White Paper: Layer 3 Forwarding and IPSec Measurement and Optimization |
39 |
White Paper: PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Cons
|
White Paper: PCB Stackup Overview for Intel® Architecture Platforms—Layout and Signal Integrity Considerations |
40 |
White Paper: Platform Software Optimization for Multi-Core Architecture Processors
|
White Paper: Platform Software Optimization for Multi-Core Architecture Processors |
41 |
White Paper: Platform-Level error Handling Strategies for Intel® Systems
|
White Paper: Platform-Level error Handling Strategies for Intel® Systems |
42 |
White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts
|
White Paper: Reducing Interrupt Latency in Embedded Systems through Message Signaled Interrupts |
43 |
White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines
|
White Paper: Signal Integrity Pitfalls When You Deviate from Intel Design Guidelines |
44 |
White Paper: The New Intel® Xeon® Processor 5500 Series Catapults Processor Performance, Scalability
|
White Paper: The New Intel® Xeon® Processor 5500 Series Catapults Processor Performance, Scalability, and Efficiency–A Huge Win for the Storage Industry |
45 |
White Paper: Using Intel® AES New Instructions and PCLMULQDQ to Significantly Improve IPSec Performa
|
White Paper: Using Intel® AES New Instructions and PCLMULQDQ to Significantly Improve IPSec Performance on Linux* |
46 |
面向嵌入式计算的英特尔® 至强® 5600/5500 系列平台
|
面向嵌入式计算的英特尔® 至强® 5600/5500 系列平台 |