On today’s SoC designs, the memory and memory arrays take up a lot of real estate and are often in the critical path for timing, yield, and schedule. Due to ever-increasing memory size demand, design and verification engineers are faced with multiple challenges, such as time to market due to an aggressive schedule, the use of different point tools such as SPICE and FastSPICE simulators, characterization utility, and the consistency that is required across the tools.
The Cadence® Legato™ Memory Solution is the industry’s first integrated solution for memory design, verification, and characterization. Eliminating the complexity of piecing together point tools for multiple design and verification tasks, Legato Memory Solution provides one platform for all memory design, verification, and characterization needs, maximizing the simulation throughput and leading to a 2X runtime improvement while maintaining the accuracy.
The new solution is built on the golden-, industry- and silicon-proven Spectre® and Liberate™ simulation and characterization engines and includes a new patent-pending Super Sweep technology that utilizes existing simulation databases for multi-corner and Monte Carlo analysis, allowing designers to improve both runtime and simulation throughput.
key benifits:
Shared engines across design and characterization ensure consistency of results
Better overall throughput through tight integration between different tools
One-stop shop for all memory design, verification, and characterization needs
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